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architecture,repository

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Marc Beninca 2021-10-10 04:50:28 +02:00 committed by Marc Beninca
parent d03d9ebcbf
commit 44e6cedaa4
2 changed files with 11 additions and 9 deletions
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6
arguments.py
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@ -72,9 +72,9 @@ compression applying to archive
action='info', action='info',
remote='https://repo.msys2.org', remote=msys.REPOSITORY,
architectures=['x86_64'], architectures=[msys.ARCHITECTURE],
subsystems=['msys', 'mingw'], subsystems=[msys.SUBSYSTEM, 'mingw'],
filesystem='fs', filesystem='fs',
compression='zst', compression='zst',

14
msys.py
View file

@ -1,18 +1,20 @@
ARCHIVE = '.tar.xz' ARCHIVE = '.tar.xz'
ARCHITECTURES = ['x86_64', 'i686'] ARCHITECTURE = 'x86_64'
ARCHITECTURES_BITS = {
'x86_64': 64,
'i686': 32,
}
CATALOG = '.files' CATALOG = '.files'
CHARSET = 'u8' CHARSET = 'u8'
CRT = 'mingw' CRT = 'mingw'
DISTRIBUTION = 'distrib' DISTRIBUTION = 'distrib'
REPOSITORY = 'https://repo.msys2.org'
SIGNATURE = '.sig' SIGNATURE = '.sig'
SUBSYSTEM = 'msys' SUBSYSTEM = 'msys'
ARCHITECTURES = [ARCHITECTURE, 'i686']
ARCHITECTURES_BITS = {
ARCHITECTURE: 64,
'i686': 32,
}
ARCHITECTURES_SUBSYSTEMS = { ARCHITECTURES_SUBSYSTEMS = {
'x86_64': [SUBSYSTEM, 'clang64', 'mingw64', 'ucrt64'], ARCHITECTURE: [SUBSYSTEM, 'clang64', 'mingw64', 'ucrt64'],
'i686': [SUBSYSTEM, 'clang32', 'mingw32'], 'i686': [SUBSYSTEM, 'clang32', 'mingw32'],
} }
SUBSYSTEMS = [SUBSYSTEM, 'clang', 'mingw', 'ucrt'] SUBSYSTEMS = [SUBSYSTEM, 'clang', 'mingw', 'ucrt']