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This commit is contained in:
Marc Beninca 2021-10-10 05:04:35 +02:00 • committed by Marc Beninca
parent b0ecc43961
commit 279cab318a
2 changed files with 18 additions and 14 deletions
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24
msys.py
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@ -22,6 +22,20 @@ ARCHITECTURES_SUBSYSTEMS = {
SUBSYSTEMS = [SUBSYSTEM, 'clang', 'mingw', 'ucrt']
def get_distribution(architecture):
return os.path.join(DISTRIBUTION, architecture)
def get_subsystem(architecture, subsystem):
list = []
if subsystem != SUBSYSTEM:
list.append(CRT)
list.append(subsystem)
if subsystem == SUBSYSTEM:
list.append(architecture)
return os.sep.join(list)
def get_subsystems(architecture, families):
list = []
bits = ARCHITECTURES_BITS[architecture]
@ -33,13 +47,3 @@ def get_subsystems(architecture, families):
if subsystem in ARCHITECTURES_SUBSYSTEMS[architecture]:
list.append(subsystem)
return list
def get_subsystem(architecture, subsystem):
list = []
if subsystem != SUBSYSTEM:
list.append(CRT)
list.append(subsystem)
if subsystem == SUBSYSTEM:
list.append(architecture)
return os.sep.join(list)